MC9S12XD256MAL Datasheet, PDF (52/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 1 Device Overview MC9S12XD-Family
1.2.2 Signal Properties Summary
Table 1-7 summarizes the pin functionality of the MC9S12XDP512. For available modules on other parts
of the S12XD, S12XB and S12XA family please refer to Appendix E Derivative Differences.
Table 1-7. Signal Properties Summary (Sheet 1 of 4)
Pin
Name
Function 1
Pin
Name
Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
Power
Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
EXTAL
—
—
—
—
V_DDPLL
NA
NA Oscillator pins
XTAL
—
—
—
—
V_DDPLL
NA
NA
RESET
—
—
—
—
V_DDR
PULLUP
External reset
TEST
—
—
—
—
N.A. RESET pin DOWN Test input
VREGEN
—
—
—
—
V_DDX
PUCR
Up Voltage regulator enable
Input
XFC
—
—
—
—
V_DDPLL
NA
NA PLL loop filter
BKGD
MODC
—
—
—
V_DDX Always on
Up Background debug
PAD[23:08] AN[23:8]
—
—
—
V_DDA
PER0/ Disabled Port AD I/O, Port AD inputs
PER1
of ATD1 and
analog inputs of ATD1
PAD[07:00] AN[7:0]
—
—
—
V_DDA
PER1 Disabled Port AD I/O, Port AD inputs
of ATD0 and
analog inputs of ATD0
PA[7:0]
—
—
—
PB[7:0]
—
—
—
PA[7:0] ADDR[15:8] IVD[15:8]
—
—
V_DDR
PUCR Disabled Port A I/O
—
V_DDR
PUCR Disabled Port BI/O
—
V_DDR
PUCR Disabled Port A I/O, address bus,
internal visibility data
PB[7:1] ADDR[7:1] IVD[7:0]
—
—
V_DDR
PUCR Disabled Port B I/O, address bus,
internal visibility data
PB0
ADDR0
UDS
V_DDR
PUCR
Disabled Port B I/O, address bus,
upper data strobe
PC[7:0] DATA[15:8]
—
—
PD[7:0] DATA[7:0]
—
—
PE7
ECLKX2 XCLKS
—
—
V_DDR
PUCR Disabled Port C I/O, data bus
—
V_DDR
PUCR Disabled Port D I/O, data bus
—
V_DDR
PUCR
Up Port E I/O, system clock
output, clock select
PE6
TAGHI
MODB
—
—
V_DDR
While RESET
Port E I/O, tag high, mode
pin is low: down input
PE5
RE
MODA TAGLO
—
V_DDR
While RESET
Port E I/O, read enable,
pin is low: down mode input, tag low input
PE4
ECLK
—
—
—
V_DDR
PUCR
PE3
LSTRB
LDS EROMCTL
—
V_DDR
PUCR
Up Port E I/O, bus clock output
Up Port E I/O, low byte data
strobe, EROMON control
PE2
R/W
WE
—
PE1
IRQ
—
—
—
V_DDR
PUCR
—
V_DDR
PUCR
Up Port E I/O, read/write
Up Port E Input, maskable
interrupt
MC9S12XDP512 Data Sheet, Rev. 2.21
52
Freescale Semiconductor