MC9S12XD256MAL Datasheet, PDF (335/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 7-38. Pulse Accumulators Count Register 2 (PACN2)
0
PACNT0
0
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
7.3.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
7
6
5
4
3
2
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
W
Reset
0
0
0
0
0
0
1
PACNT1(9)
0
Figure 7-39. Pulse Accumulators Count Register 1 (PACN1)
0
PACNT0(8)
0
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 7-40. Pulse Accumulators Count Register 0 (PACN0)
0
PACNT0
0
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents
are respectively the high and low byte of the PACB.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
335