MC9S12XD256MAL Datasheet, PDF (667/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.3.2.8 Program Page Index Register (PPAGE)
Address: 0x0030
R
W
Reset
7
PIX7
1
6
PIX6
5
PIX5
4
PIX4
3
PIX3
2
PIX2
1
1
1
1
1
Figure 18-15. Program Page Index Register (PPAGE)
1
PIX1
1
0
PIX0
0
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 18-16). This supports
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE age
index register is effectively used to construct paged Flash addresses in the Local map format. The CPU has
special access to read and write this register directly during execution of CALL and RTC instructions. .
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
1 Bit21
Bit14 Bit13
Bit0
PPAGE Register [7:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 18-16. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
667