MC9S12XD256MAL Datasheet, PDF (255/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

CSL
Logical Shift Left with Carry
Chapter 6 XGATE (S12XGATEV2)
CSL
Operation
n
C
RD
CCCC
n bits
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]_old ^ RD[15]_new
C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
CSL RD, #IMM4
CSL RD, RS
Address
Mode
IMM4
DYA
00001
00001
Machine Code
Cycles
RD
IMM4
1010
P
RD
RS 1 0 0 1 0
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
255