MC9S12XD256MAL Datasheet, PDF (642/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.4.4 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 1-26).
BDM
CPU
XGATE
S12X
S12X
XGATE
MMC
XRAM ^XBus2
XBus1
EBI
BDM
ROM/REG
XBus0
RAM
XEEPROM
XFLASH
IPBI
P3
P2
P1
P0
IO
2 Kbyte Registers
Figure 17-26. S12X Architecture
17.4.4.1 Master Bus Prioritization
The following rules apply when prioritizing accesses over master buses:
• The CPU has priority over the BDM, unless the BDM access is stalled for more than 128 cycles.
In the later case the CPU will be stalled after finishing the current operation and the BDM will gain
access to the bus.
• XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
and BDM for its duration.
MC9S12XDP512 Data Sheet, Rev. 2.21
642
Freescale Semiconductor