MC9S12XD256MAL Datasheet, PDF (635/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Bit22
Chapter 17 Memory Mapping Control (S12XMMCV2)
BDM HARDWARE COMMAND
Global Address [22:0]
Bit16 Bit15
Bit0
BDMGPR Register [6:0]
BDM Local Address
Bit22
BDM FIRMWARE COMMAND
Global Address [22:0]
Bit16 Bit15
Bit0
BDMGPR Register [6:0]
CPU Local Address
Figure 17-22. BDMGPR Address Mapping
17.4.2.3 Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, EEPROM, and FLASH) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the Device User Guide for further details.
Figure 17-23 and Table 17-20 show the memory spaces occupied by the on-chip resources. Please note that
the memory spaces have fixed top addresses.
Table 17-19. Global Implemented Memory Space
Internal Resource
Bottom Address
Registers
$00_0000
RAM
$10_0000 minus RAMSIZE¹
EEPROM
$14_0000 minus EEPROMSIZE²
FLASH
$80_0000 minus FLASHSIZE³
1 _{RAMSIZE is the hexadecimal value of RAM SIZE in bytes}
2 _{EEPROMSIZE is the hexadecimal value of EEPROM SIZE in bytes}
3 _{FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes}
Top Address
$00_07FF
$0F_FFFF
$13_FFFF
$7F_FFFF
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
635