MC9S12XD256MAL Datasheet, PDF (542/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
PIT operation in wait mode is controlled by the PITSWAI bit located in the PITCFLMT register.
In wait mode, if the bus clock is globally enabled and if the PITSWAI bit is clear, the PIT operates
like in run mode. In wait mode, if the PITSWAI bit is set, the PIT module is stalled.
• Stop mode
In full stop mode or pseudo stop mode, the PIT module is stalled.
• Freeze mode
PIT operation in freeze mode is controlled by the PITFRZ bit located in the PITCFLMT register.
In freeze mode, if the PITFRZ bit is clear, the PIT operates like in run mode. In freeze mode, if the
PITFRZ bit is set, the PIT module is stalled.
13.1.4 Block Diagram
Figure 13-1 shows a block diagram of the PIT.
Bus Clock
8-Bit
Micro Timer 0
Micro Time
Base 0
8-Bit
Micro Timer 1
Micro
Time
Base 1
16-Bit Timer 0
16-Bit Timer 1
16-Bit Timer 2
Time-Out 0
Time-Out 1
Time-Out 2
Interrupt 0
Interface _{Trigger 0}
Interrupt 1
Interface _{Trigger 1}
Interrupt 2
Interface _{Trigger 2}
16-Bit Timer 3
Time-Out 3
Interrupt 3
Interface _{Trigger 3}
Figure 13-1. PIT Block Diagram
13.2 External Signal Description
The PIT module has no external pins.
MC9S12XDP512 Data Sheet, Rev. 2.21
542
Freescale Semiconductor