MC9S12XD256MAL Datasheet, PDF (334/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
7
6
5
4
3
2
1
R
0
0
0
0
0
0
PAOVF
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-36. Pulse Accumulator A Flag Register (PAFLG)
0
PAIF
0
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 7-21. PAFLG Field Descriptions
Field
1
PAOVF
0
PAIF
Description
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on PT3.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the PT7 input pin triggers PAIF.
7.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
7
6
5
4
3
2
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
W
Reset
0
0
0
0
0
0
1
PACNT1(9)
0
Figure 7-37. Pulse Accumulators Count Register 3 (PACN3)
0
PACNT0(8)
0
MC9S12XDP512 Data Sheet, Rev. 2.21
334
Freescale Semiconductor