MC9S12XD256MAL Datasheet, PDF (959/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

23.0.5.71 Port AD1 Reduced Drive Register 1 (RDR1AD1)
7
6
5
4
3
2
1
R
RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19
W
0
RDR1AD18
Reset
0
0
0
0
0
0
0
0
Figure 23-73. Port AD1 Reduced Drive Register 1 (RDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[15:8] output pin as either full or reduced.
If the port is used as input this bit is ignored.
Table 23-64. RDR1AD1 Field Descriptions
Field
Description
7–0
Reduced Drive Port AD1 Register 1
RDR1AD1[15:8] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
23.0.5.72 Port AD1 Pull Up Enable Register 0 (PER0AD1)
7
6
5
4
3
2
1
0
R
PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116
W
Reset
0
0
0
0
0
0
0
0
Figure 23-74. Port AD1 Pull Up Enable Register 0 (PER0AD1)
Read: Anytime.
Write: Anytime.
This register activates a pull-up device on the respective PAD[23:16] pin if the port is used as input.
This bit has no effect if the port is used as output. Out of reset no pull-up device is enabled.
Table 23-65. PER0AD1 Field Descriptions
Field
7–0
Pull Device Enable Port AD1 Register 0
PER0AD1[23:16] 0 Pull-up device is disabled.
1 Pull-up device is enabled.
Description