MC9S12XD256MAL Datasheet, PDF (949/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 23-49. PIEH Field Descriptions
Field
Description
7–0
PIEH[7:0]
Interrupt Enable Port H
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
23.0.5.53 Port H Interrupt Flag Register (PIFH)
7
R
PIFH7
W
6
PIFH6
5
PIFH5
4
PIFH4
3
PIFH3
2
PIFH2
1
PIFH1
0
PIFH0
Reset
0
0
0
0
0
0
0
0
Figure 23-55. Port H Interrupt Flag Register (PIFH)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling
edge based on the state of the PPSH register. To clear this flag, write logic level “1” to the
corresponding bit in the PIFH register. Writing a “0” has no effect.
Table 23-50. PIFH Field Descriptions
Field
Description
7–0
PIFH[7:0]
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.