MC9S12XD256MAL Datasheet, PDF (722/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format
for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal
or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the
DBGCNT[0] is incremented after each separate entry. In all other modes, DBGCNT[0] remains cleared
while the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and S12X_CPU COFs occur independently of each other and the profile of COFs for the 2 sources
is totally different. When both sources are being traced in Normal or Loop1 mode, for each single entry
from one source, there may be many entries from the other source and vice versa, depending on user code.
COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously.
If a COF occurs in one source only in a particular cycle, then the trace buffer bytes that are mapped to the
other source are redundant. Info byte bit CDV/XDV indicates that no useful information is stored in these
bytes. This is the typical case. Only in the rare event that both XGATE and S12X_CPU COF cycles
coincide is a valid trace buffer entry for both made, corresponding to the first line for mode "Both
Normal/Loop1" in Table 19-39.
Single byte data accesses in detail mode are always stored to the low byte of the trace buffer (CDATAL or
XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always
stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Table 19-39. Trace Buffer Organization
Mode
XGATE DETAIL
7
CXINF1
CXINF2
6
CADRH1
CADRH2
8-Byte Wide Word Buffer
5
CADRM1
CADRM2
4
CADRL1
CADRL2
3
XDATAH1
XDATAH2
2
XDATAL1
XDATAL2
1
XADRM1
XADRM2
0
XADRL1
XADRL2
CPU
DETAIL
CXINF1
CXINF2
CADRH1
CADRH2
CADRM1
CADRM2
CADRL1
CADRL2
CDATAH1
CDATAH2
CDATAL1
CDATAL2
XADRM1
XADRM2
XADRL1
XADRL2
Both
NORMAL
/ LOOP1
XINF0
1_XINF1
2_XINF2
XADRM0 XADRL0
XADRM2 XADRL2
CINF0
CINF1
CINF2
CADRH0
CADRH1
CADRM0
CADRM1
CADRL0
CADRL1
XGATE
NORMAL
/ LOOP1
XINF1
XINF3
XADRM1
XADRM3
XADRL1
XADRL3
XINF0
XINF2
XADRM0
XADRM2
XADRL0
XADRL2
CPU
NORMAL
/ LOOP1
CINF1
CINF3
CADRH1
CADRH3
CADRM1
CADRM3
CADRL1
CADRL3
CINF0
CINF2
1 _{COF in CPU only. XGATE trace buffer entries in this tracing step are invalid}
2 _{COF in XGATE only. CPU trace buffer entries in this tracing step are invalid}
CADRH0
CADRH2
CADRM0
CADRM2
CADRL0
CADRL2
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor