MC9S12XD256MAL Datasheet, PDF (912/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-3. Pin Configuration Summary
DDR
IO
RDR
PE
PS¹
IE²
Function
0
x
x
0
x
0
Input
0
x
x
1
0
0
Input
0
x
x
1
1
0
Input
0
x
x
0
0
1
Input
0
x
x
0
1
1
Input
0
x
x
1
0
1
Input
0
x
x
1
1
1
Input
1
0
0
x
x
0
Output, full drive to 0
1
1
0
x
x
0
Output, full drive to 1
1
0
1
x
x
0
Output, reduced drive to 0
1
1
1
x
x
0
Output, reduced drive to 1
1
0
0
x
0
1
Output, full drive to 0
1
1
0
x
1
1
Output, full drive to 1
1
0
1
x
0
1
Output, reduced drive to 0
1
1
1
x
1
1
Output, reduced drive to 1
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
Pull Device
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Interrupt
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
Register
Name
Bit 7
6
5
4
3
2
PORTA R
PA7
PA6
PA5
PA4
PA3
PA2
W
PORTB R
PB7
PB6
PB5
PB4
PB3
PB2
W
DDRA R
DDRA7
W
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRB R
DDRB7
W
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
= Unimplemented or Reserved
Figure 23-2. PIM Register Summary (Sheet 1 of 7)
1
PA1
PB1
DDRA1
DDRB1
Bit 0
PA0
PB0
DDRA0
DDRB0
MC9S12XDP512 Data Sheet, Rev. 2.21
914
Freescale Semiconductor