MC9S12XD256MAL Datasheet, PDF (947/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 23-45. DDRH Field Descriptions
Field
Description
7–0
DDRH[7:0]
Data Direction Port H
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTH or PTIH registers, when changing the DDRH register.
23.0.5.49 Port H Reduced Drive Register (RDRH)
R
W
Reset
7
RDRH7
0
6
RDRH6
5
RDRH5
4
RDRH4
3
RDRH3
2
RDRH2
0
0
0
0
0
Figure 23-51. Port H Reduced Drive Register (RDRH)
1
RDRH1
0
0
RDRH0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port H output pin as either full or reduced. If the
port is used as input this bit is ignored.
Table 23-46. RDRH Field Descriptions
Field
Description
7–0
Reduced Drive Port H
RDRH[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
23.0.5.50 Port H Pull Device Enable Register (PERH)
R
W
Reset
7
PERH7
0
6
PERH6
5
PERH5
4
PERH4
3
PERH3
2
PERH2
1
PERH1
0
0
0
0
0
0
Figure 23-52. Port H Pull Device Enable Register (PERH)
0
PERH0
0
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as
input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.