MC9S12XD256MAL Datasheet, PDF (946/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.47 Port H Input Register (PTIH)
7
R PTIH7
6
PTIH6
5
PTIH5
4
PTIH4
3
PTIH3
2
PTIH2
1
PTIH1
0
PTIH0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 23-49. Port H Input Register (PTIH)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
23.0.5.48 Port H Data Direction Register (DDRH)
7
R
DDRH7
W
6
DDRH6
5
DDRH5
4
DDRH4
3
DDRH3
2
DDRH2
1
DDRH1
0
DDRH0
Reset
0
0
0
0
0
0
0
0
Figure 23-50. Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated routed SPI module is enabled this register has no effect on the pins.
The SCI forces the I/O state to be an output for each port line associated with an enabled output ( TXD4).
It also forces the I/O state to be an input for each port line associated with an enabled input ( RXD4). In
those cases the data direction bits will not change.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are
disabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
948
Freescale Semiconductor