MC9S12XD256MAL Datasheet, PDF (704/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 19-21. State1 Sequencer Next Sate Selection
Description
Any match triggers to state2
Any match triggers to state3
Any match triggers to final state
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
Match2 triggers to final state....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers final state....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers to final state....... Other matches have no effect
Reserved
Reserved
Reserved
Reserved
19.3.1.9 Debug State Control Register 2 (DBGSCR2)
0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 19-11. Debug State Control Register 2 (DBGSCR2)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state while in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 19-1 and described in Section 19.3.1.11.1, “Debug Comparator Control
Register (DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the
associated DBGXCTL control register.
MC9S12XDP512 Data Sheet, Rev. 2.21
706
Freescale Semiconductor