MC9S12XD256MAL Datasheet, PDF (855/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.40 Port P Data Direction Register (DDRP)
R
W
Reset
7
DDRP7
0
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 22-42. Port P Data Direction Register (DDRP)
1
DDRP1
0
0
DDRP0
0
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0
channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for
details.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.
Table 22-39. DDRP Field Descriptions
Field
Description
7–0
DDRP[7:0]
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTP or PTIP registers, when changing the DDRP register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
857