MC9S12XD256MAL Datasheet, PDF (486/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
11.3.2.4 SCI Alternative Control Register 1 (SCIACR1)
R
W
Reset
7
RXEDGIE
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-7. SCI Alternative Control Register 1 (SCIACR1)
1
BERRIE
0
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 11-6. SCIACR1 Field Descriptions
0
BKDIE
0
Field
Description
7
RSEDGIE
1
BERRIE
0
BKDIE
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
MC9S12XDP512 Data Sheet, Rev. 2.21
486
Freescale Semiconductor