MC9S12XD256MAL Datasheet, PDF (401/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 9-5. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
IBC[7:0]
(hex)
MUL=1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
Table 9-5. IIC Divider and Hold Values (Sheet 1 of 5)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
20
7
6
22
7
7
24
8
8
26
8
9
28
9
10
30
9
11
34
10
13
40
10
16
28
7
10
32
7
12
36
9
14
40
9
16
44
11
18
48
11
20
56
13
24
68
13
30
48
9
18
56
9
22
64
13
26
72
13
30
80
17
34
88
17
38
104
21
46
128
21
58
80
9
38
96
9
46
112
17
54
128
17
62
144
25
70
160
25
78
192
33
94
240
33
118
160
17
78
192
17
94
224
33
110
SCL Hold
(stop)
11
12
13
14
15
16
18
21
15
17
19
21
23
25
29
35
25
29
33
37
41
45
53
65
41
49
57
65
73
81
97
121
81
97
113
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
401