MC9S12XD256MAL Datasheet, PDF (624/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
Table 17-10. Data Sources when CPU or BDM is Accessing Flash Area
Chip Modes
ROMON
EROMON
DATA SOURCE¹
Stretch²
Normal Single Chip
X
X
Internal
N
Special Single Chip
Emulation Single Chip
X
0
Emulation Memory
N
X
1
Internal Flash
Normal Expanded
0
X
External Application
Y
1
X
Internal Flash
N
Emulation Expanded
0
X
External Application
Y
1
0
Emulation Memory
N
1
1
Internal Flash
Special Test
0
X
External Application
N
1
X
Internal Flash
1 _{Internal means resources inside the MCU are read/written.}
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, flash
replacement, RAM, EEPROM and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
2 _{The external access stretch mechanism is part of the EBI module (refer to EBI Block Guide for details).}
17.3.2.6 RAM Page Index Register (RPAGE)
Address: 0x0016
R
W
Reset
7
RP7
1
6
RP6
1
5
RP5
1
4
RP4
1
3
RP3
1
2
RP2
1
1
RP1
0
0
RP0
1
Figure 17-11. RAM Page Index Register (RPAGE)
Read: Anytime
Write: Anytime
The RAM page index register allows accessing up to (1M minus 2K) bytes of RAM in the global memory
map by using the eight page index bits to page 4 Kbyte blocks into the RAM page window located in the
CPU local memory map from address $1000 to address $1FFF (see Figure 1-12).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
MC9S12XDP512 Data Sheet, Rev. 2.21
624
Freescale Semiconductor