MC9S12XD256MAL Datasheet, PDF (869/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.57 Port J Reduced Drive Register (RDRJ)
R
W
Reset
7
RDRJ7
0
6
5
4
3
2
0
RDRJ6
RDRJ5
RDRJ4
RDRJ2
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-59. Port J Reduced Drive Register (RDRJ)
1
RDRJ1
0
0
RDRJ0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 22-53. RDRJ Field Descriptions
Field
Description
7–0
Reduced Drive Port J
RDRJ[7:4] 0 Full drive strength at output.
RDRJ[2:0] 1 Associated pin drives at about 1/6 of the full drive strength.
22.3.2.58 Port J Pull Device Enable Register (PERJ)
R
W
Reset
7
PERJ7
1
6
5
4
3
2
0
PERJ6
PERJ5
PERJ4
PERJ2
1
1
1
0
1
= Unimplemented or Reserved
Figure 22-60. Port J Pull Device Enable Register (PERJ)
1
PERJ1
1
0
PERJ0
1
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up
device is enabled.
Table 22-54. PERJ Field Descriptions
Field
Description
7–0
Pull Device Enable Port J
PERJ[7:4] 0 Pull-up or pull-down device is disabled.
PERJ[2:0] 1 Either a pull-up or pull-down device is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
871