MC9S12XD256MAL Datasheet, PDF (774/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
20.4.5.1.3 Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point
the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the
address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
20.4.5.2 Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in
the DBGTCR register. In each mode tracing of XGATE or S12XCPU information is possible. The source
for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the
following subsections. The trace buffer organization is shown in Table 20-39.
20.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows for the S12XCPU:
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction.
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for SWI and BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
• Source address of taken conditional branches
• Destination address of indexed JAL instructions.
• First XGATE code address in a thread
Change-of-flow addresses stored include the full 23-bit address bus in the case of S12XCPU, the 16-bit
address bus for the XGATE module and an information byte, which contains a source/destination bit to
indicate whether the stored address was a source address or destination address.
20.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
S12XDBG module writes this value into a background register. This prevents consecutive duplicate
address entries in the Trace Buffer resulting from repeated branches.
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor