MC9S12XD256MAL Datasheet, PDF (696/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
Address
Register
Name
Bit 7
6
5
4
3
2
0x0029 DBGXAH R
0
Bit 22
21
20
19
18
W
0x002A DBGXAM R
Bit 15
14
13
12
11
10
W
0x002B DBGXAL R
Bit 7
6
5
4
3
2
W
0x002C DBGXDH R
Bit 15
14
13
12
11
10
W
0x002D DBGXDL R
Bit 7
6
5
4
3
2
W
0x002E DBGXDHM R
Bit 15
14
13
12
11
10
W
0x002F DBGXDLM R
Bit 7
6
5
4
3
2
W
= Unimplemented or Reserved
Figure 19-2. DBG Register Summary (continued)
1
Bit 0
17
Bit 16
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
19.3.1.1 Debug Control Register 1 (DBGC1)
0x0020
R
W
Reset
7
ARM
0
6
0
TRIG
0
5
XGSBPE
0
4
BDM
0
3
2
DBGBRK
0
0
1
0
COMRV
0
0
Read: Anytime
Figure 19-3. Debug Control Register (DBGC1)
Write: Bits 7,1,0 anytime, Bit 6 can be written anytime but always reads back as 0.
Bits 5:2 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[5:2] are not affected by the write, since up until the write operation,
ARM=1 preventing these bits from being written. These bits must be cleared
using a second write if required.
MC9S12XDP512 Data Sheet, Rev. 2.21
698
Freescale Semiconductor