MC9S12XD256MAL Datasheet, PDF (1033/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

24.0.9.2 Wait Mode
No low-power options exist for this module in wait mode.
24.0.9.3 Stop Mode
All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H,
and J.
Initialization and Application Information
• It is not recommended to write PORTx and DDRx in a word access. When changing the
register pins from inputs to outputs, the data may have extra transitions during the write
access. Initialize the port data register before enabling the outputs.
• Power consumption will increase the more the voltages on general purpose input pins
deviate from the supply voltages towards mid-range because the digital input buffers
operate in the linear region.