MC9S12XD256MAL Datasheet, PDF (950/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.54 Port J Data Register (PTJ)
7
6
5
4
3
2
1
0
R
0
PTJ7
PTJ6
PTJ5
PTJ4
PTJ2
PTJ1
PTJ0
W
CAN4 TXCAN4 RXCAN4
SCI2
TXD2
RXD2
IIC0 SCL0
SDA0
Routed
CAN0
TXCAN0
RXCAN0
Alt.
Function
CS2
CS0
CS1
CS3
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-56. Port J Data Register (PTJ)
Read: Anytime.
Write: Anytime.
Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0, the routed CAN0 modules and chip
select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not used with
any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
Table 23-51. PTJ Field Descriptions
Field
7–6
PJ[7:6]
2
PJ2
1
PJ1
0
PJ0
Description
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured
as open drain outputs. Refer to IIC section for details.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if
the routed CAN0 module is enabled. Refer to MSCAN section for details.
The chip select function (CS1) takes precedence over the general purpose I/O.
The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer
to SCI section for details.
The chip select (CS3) takes precedence over the general purpose I/O function.
MC9S12XDP512 Data Sheet, Rev. 2.21
952
Freescale Semiconductor