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MC9S12XD256MAL Datasheet, PDF (441/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
10.3.2.17 MSCAN Identiï¬er Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identiï¬er acceptance and identiï¬er mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0âIDR3 registers (see Section 10.3.3.1,
âIdentiï¬er Registers (IDR0âIDR3)â) of incoming messages in a bit by bit manner (see Section 10.4.3,
âIdentiï¬er Acceptance Filterâ).
For extended identiï¬ers, all four acceptance and mask registers are applied. For standard identiï¬ers, only
the ï¬rst two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 (CANIDAR0)
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
7
R
AC7
W
6
AC6
5
AC5
4
AC4
3
AC3
2
AC2
1
AC1
0
AC0
Reset
0
0
0
0
0
0
0
0
Figure 10-20. MSCAN Identiï¬er Acceptance Registers (First Bank) â CANIDAR0âCANIDAR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
441
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