MC9S12XD256MAL Datasheet, PDF (993/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 24-8. PORTE Field Descriptions
Field
7–0
PE[7:0]
Description
Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include
mode select (MODB, MODA), E clock, double frequency E clock, IRQ, and XIRQ.
When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and
pins 1–0 can be used as general purpose inputs.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
24.0.5.6 Port E Data Direction Register (DDRE)
7
6
5
4
3
2
1
0
R
0
0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-8. Port E Data Direction Register (DDRE)
Read: Anytime.
Write: Anytime.
Table 24-9. DDRE Field Descriptions
Field
Description
7–0
DDRE[7:2]
Data Direction Port E — his register controls the data direction for port E. DDRE determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits
1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTE after changing the DDRE register.