MC9S12XD256MAL Datasheet, PDF (845/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.28 Port S Polarity Select Register (PPSS)
R
W
Reset
7
PPSS7
0
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
0
0
0
0
0
Figure 22-30. Port S Polarity Select Register (PPSS)
1
PPSS1
0
0
PPSS0
0
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 22-30. PPSS Field Descriptions
Field
Description
7–0
PPSS[7:0]
Pull Select Port S
0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input or as wired-OR output.
1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input.
22.3.2.29 Port S Wired-OR Mode Register (WOMS)
R
W
Reset
7
WOMS7
0
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
1
WOMS1
0
0
0
0
0
0
Figure 22-31. Port S Wired-OR Mode Register (WOMS)
0
WOMS0
0
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a
multipoint connection of several serial modules. These bits have no influence on pins used as inputs.
Table 22-31. WOMS Field Descriptions
Field
Description
7–0
Wired-OR Mode Port S
WOMS[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
847