MC9S12XD256MAL Datasheet, PDF (183/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6
XGATE (S12XGATEV2)
6.1 Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 6-1 gives an overview on the XGATE architecture.
This document describes the functionality of the XGATE module, including:
• XGATE registers (Section 6.3, “Memory Map and Register Definition”)
• XGATE RISC core (Section 6.4.1, “XGATE RISC Core”)
• Hardware semaphores (Section 6.4.4, “Semaphores”)
• Interrupt handling (Section 6.5, “Interrupts”)
• Debug features (Section 6.6, “Debug Mode”)
• Security (Section 6.7, “Security”)
• Instruction set (Section 6.8, “Instruction Set”)
6.1.1 Glossary of Terms
XGATE Request
A service request from a peripheral module which is directed to the XGATE by the S12X_INT
module (see Figure 6-1).
XGATE Channel
The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request
Vector, Interrupt Flag) which are associated with a particular XGATE Request.
XGATE Channel ID
A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range
from $78 to $09.
XGATE Channel Interrupt
An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module.
XGATE Software Channel
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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