MC9S12XD256MAL Datasheet, PDF (1000/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
Table 24-19. DDRT Field Descriptions
Field
Description
7–0
DDRT[7:0]
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTT or PTIT registers, when changing the DDRT register.
24.0.5.16 Port T Reduced Drive Register (RDRT)
R
W
Reset
7
RDRT7
0
6
RDRT6
5
RDRT5
4
RDRT4
3
RDRT3
2
RDRT2
0
0
0
0
0
Figure 24-18. Port T Reduced Drive Register (RDRT)
1
RDRT1
0
0
RDRT0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 24-20. RDRT Field Descriptions
Field
Description
7–0
Reduced Drive Port T
RDRT[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.17 Port T Pull Device Enable Register (PERT)
R
W
Reset
7
PERT7
0
Read: Anytime.
Write: Anytime.
6
PERT6
5
PERT5
4
PERT4
3
PERT3
2
PERT2
1
PERT1
0
0
0
0
0
0
Figure 24-19. Port T Pull Device Enable Register (PERT)
0
PERT0
0
1002
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor