MC9S12XD256MAL Datasheet, PDF (1003/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Table 24-23. DDRS Field Descriptions
Field
Description
7–0
DDRS[7:0]
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTS or PTIS registers, when changing the DDRS register.
24.0.5.22 Port S Reduced Drive Register (RDRS)
R
W
Reset
7
RDRS7
0
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 24-24. Port S Reduced Drive Register (RDRS)
1
RDRS1
0
0
RDRS0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the
port is used as input this bit is ignored.
Table 24-24. RDRS Field Descriptions
Field
Description
7–0
Reduced Drive Port S
RDRS[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
24.0.5.23 Port S Pull Device Enable Register (PERS)
R
W
Reset
7
PERS7
1
Read: Anytime.
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
1
1
1
1
Figure 24-25. Port S Pull Device Enable Register (PERS)
1
PERS1
1
0
PERS0
1