MC9S12XD256MAL Datasheet, PDF (325/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

7.3.2.9
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
R
W
Reset
7
EDG7B
0
6
EDG7A
5
EDG6B
4
EDG6A
3
EDG5B
2
EDG5A
0
0
0
0
0
Figure 7-13. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
R
W
Reset
7
EDG3B
0
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
0
0
0
0
0
Figure 7-14. Timer Control Register 4 (TCTL4)
Read or write: Anytime
All bits reset to zero.
Table 7-11. TCTL3/TCTL4 Field Descriptions
1
EDG0B
0
0
EDG0A
0
Field
Description
EDG[7:0]B
7, 5, 3, 1
EDG[7:0]A
6, 4, 2, 0
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture
edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See Table 7-12.
Table 7-12. Edge Detector Circuit Configuration
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
325