MC9S12XD256MAL Datasheet, PDF (320/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.4 Output Compare 7 Data Register (OC7D)
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 7-6. Output Compare 7 Data Register (OC7D)
Read or write: Anytime
All bits reset to zero.
Table 7-5. OC7D Field Descriptions
1
OC7D1
0
0
OC7D0
0
Field
Description
7:0
Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data
OC7D[7:0] register to transfer to the timer port data register depending on the output compare 7 mask register.
MC9S12XDP512 Data Sheet, Rev. 2.21
320
Freescale Semiconductor