HD64F2638F20J Datasheet, PDF (991/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
• Clearing with the STBY pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
23A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the
oscillation stabilization time).
Table 23A-5 shows the standby times for different operating frequencies and settings of bits STS2
to STS0.
Table 23A-5 Oscillation Stabilization Time Settings
STS2 STS1 STS0 Standby Time
0
0
0
8192 states
1
16384 states
1
0
32768 states
1
65536 states
1
0
0
131072 states
1
262144 states
1
0
Reserved
1
16 states
(Setting
prohibited)
: Recommended time setting
20 16 12 10 8 6 4
MHz MHz MHz MHz MHz MHz MHz Unit
0.41 0.51 0.68 0.8 1.0 1.3 2.0 ms
0.82 1.0 1.3 1.6 2.0 2.7 4.1
1.6 2.0 2.7 3.3 4.1 5.5 8.2
3.3 4.1 5.5 6.6 8.2 10.9 16.4
6.6 8.2 10.9 13.1 16.4 21.8 32.8
13.1 16.4 21.8 26.2 32.8 43.6 65.6
— — — — — — — µs
0.8 1.0 1.3 1.6 2.0 2.6 4.0
Using a External Clock: The PLL circuit requires time to stabilize, so the standby time should be
set to a value of 2 ms or more.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 941 of 1458