HD64F2638F20J Datasheet, PDF (885/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
21B.10.3 Error Protection
In error protection, an error is detected when chip runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the chip malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However,
PV and EV bit setting is enabled, and a transition can be made to verify mode.
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the CPU releases the bus to the DTC
Error protection is released only by a reset and in hardware standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 835 of 1458