HD64F2638F20J Datasheet, PDF (880/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21B ROM
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait (tspsu) μs
Set P bit in FLMCR1
Wait (tsp) μs
Clear P bit in FLMCR1
Wait (tcp) μs
*7
Start of programming
*5*7
End of programming
*7
Start of programming
START
Set SWE bit in FLMCR1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Wait (tsswe) μs
*7
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
m=0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
*1
Sub-Routine-Call
Write pulse
See Note 6 for pulse width
Clear PSU bit in FLMCR1
Wait (tcpsu) μs
*7
Disable WDT
End Sub
Set PV bit in FLMCR1
Wait (tspv) μs
*7
H'FF dummy write to verify address
Wait (tspvr) μs
*7
Read verify data
*2
n←n+1
Note: 6 Write Pulse Width
Number of Writes n Write Time (tsp) μsec
1
30
2
30
3
30
4
30
5
30
6
30
7
200
8
200
9
200
10
200
11
200
12
200
13
200
Increment address
998
200
999
200
1000
200
Note: Use a 10 μs write pulse for additional programming.
Write data =
No
verify data?
Yes
No
6≥n?
Yes
Additional-programming data computation
m=1
Transfer additional-programming data to
additional-programming data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram data area *4
128-byte
No
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait (tcpv) μs
*7
No
6 ≥ n?
RAM
Program data storage
area (128 bytes)
Yes
Successively write 128-byte data from additional-
programming data area in RAM to flash memory ^*1
Sub-Routine-Call
Write Pulse (Additional programming)
Reprogram
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
No
m=0?
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) μs
*7
*7 _No
n ≥ (N)?
Yes
Clear SWE bit in FLMCR1
Wait (tcswe) μs
*7
End of programming
Programming failure
Notes: 1.
2.
3.
4.
5.
7.
Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Verify data is read in 16-bit (word) units.
Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
A write pulse of 30 μs or 200 μs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 μs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
The wait times and value of N are shown in section 24.2.7, 24.3.7, and 24.4.7, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data
(D)
Verify Data
(V)
Reprogram Data
(X)
0
0
1
0
1
0
1
0
1
1
1
1
Comments
Programming completed
Programming incomplete;
reprogram
Still in erased state; no action
Additional-Programming Data Computation Table
Reprogram Data Verify Data
Additional-
(X')
(V)
Programming Data (Y)
Comments
0
0
0
1
0
Additional programming
to be executed
1
Additional programming
not to be executed
1
0
1
1
1
Additional programming
not to be executed
1
Additional programming
not to be executed
Figure 21B-12 Program/Program-Verify Flowchart
Page 830 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010