HD64F2638F20J Datasheet, PDF (1482/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
*1
*3
P34
*2
Reset
R
QD
P34DDR
C
WDDR3
Reset
R
QD
P34DR
C
WDR3
Reset
R
QD
P34ODR
C
WODR3
RODR3
RDR3
SCI module
Serial receive
data enable
RPOR3
Serial receive data
RxD1
IIC0 module^*4
SDA0 output
IIC0 output enable
SDA0 Input
Legend:
WDDR3: Write to P3DDR
WDR3: Write to P3DR
WODR3: Write to P3ODR
RDR3: Read P3DR
RPOR3: Read port 3
RODR3: Read P3ODR
Notes: 1. Output enable signal
2. Open drain control signal
3. Priority order: IIC output > DR output
4. The IIC0 module is available as an option in the
H8S/2638, H8S/2639, H8S/2630.
Figure C-2 (e) Port 3 Block Diagram (Pin P34)
Page 1432 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010