HD64F2638F20J Datasheet, PDF (191/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 6 PC Break Controller (PBC)
Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus
master.
Bit 6
CDA
0
1
Description
PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master
(Initial value)
Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits
specify which bits of the break address (BAA23 to BAA0) set in BARA are to be masked.
Bit 5
Bit 4
Bit 3
BAMRA2 BAMRA1 BAMRA0 Description
0
0
0
All BARA bits are unmasked and included in break conditions
(Initial value)
1
BAA0 (lowest bit) is masked, and not included in break
conditions
1
0
BAA1, BAA0 (lower 2 bits) are masked, and not included in
break conditions
1
BAA2 to BAA0 (lower 3 bits) are masked, and not included in
break conditions
1
0
0
BAA3 to BAA0 (lower 4 bits) are masked, and not included in
break conditions
1
BAA7 to BAA0 (lower 8 bits) are masked, and not included in
break conditions
1
0
BAA11 to BAA0 (lower 12 bits) are masked, and not included in
break conditions
1
BAA15 to BAA0 (lower 16 bits) are masked, and not included in
break conditions
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 141 of 1458