HD64F2638F20J Datasheet, PDF (1488/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Reset
R
Q
D
PA2PCR
C
WPCRA
RPCRA
RxD input
enable
*1
PA2
*2
Modes 4/5/6
Address
enable
Reset
R
Q
D
PA2DDR
C
WDDRA
Reset
R
Q
D
PA2DR
C
WDRA
Reset
R
Q
D
PA2ODR
C
WODRA
RODRA
RDRA
RxD input
RPORA
Legend:
WDDRA: Write to PADDR
WDRA: Write to PADR
WODRA: Write to PAODR
WPCRA: Write to PAPCR
RDRA: Read PADR
RPORA: Read port A
RODRA: Read PAODR
RPCRA: Read PAPCR
Notes: 1. Output enable signal
2. Open drain control signal
Figure C-5 (c) Port A Block Diagram (Pin PA2)
Page 1438 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010