HD64F2638F20J Datasheet, PDF (480/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Watchdog Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
12.2.2 Timer Control/Status Register (TCSR)
TCSR0
Bit
:
7
6
5
4
3
OVF WT/IT TME
—
—
Initial value :
0
0
0
1
1
R/W
: R/(W)^* R/W
R/W
—
—
Note: * Only a 0 may be written to this bit to clear the flag.
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCSR1
Bit
:
Initial value :
R/W
:
7
OVF
0
R/(W)^*1
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS^*2
0
R/W
3
RST/NMI
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Notes: 1. Only a 0 may be written to this bit to clear the flag.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in
the U-mask and W-mask versions, and H8S/2635 Group only.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 12.2.4, Notes on Register Access.
Page 430 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010