HD64F2638F20J Datasheet, PDF (443/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T₁ state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 10-53 shows the timing in this case.
TGR read cycle
T₁
T₂
φ
Address
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal
M
data bus
Figure 10-53 Contention between TGR Read and Input Capture
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 393 of 1458