HD64F2638F20J Datasheet, PDF (653/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
Stop condition
(a)
ICDR reading
prohibited
Start condition
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 15-21 Points for Attention Concerning Reading of Master Receive Data
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 603 of 1458