HD64F2638F20J Datasheet, PDF (437/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC* is activated, the flag is cleared automatically. Figure 10-46 shows the
timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag
clearing by the DTC.
Note: * The DTC is not implemented in the H8S/2635 Group.
TSR write cycle
T₁
T₂
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 10-46 Timing for Status Flag Clearing by CPU
DTC
read cycle
T₁
T₂
DTC
write cycle
T₁
T₂
φ
Address
Status flag
Source address
Destination
address
Interrupt
request
signal
Figure 10-47 Timing for Status Flag Clearing by DTC Activation
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 387 of 1458