HD64F2638F20J Datasheet, PDF (446/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence.
Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
Counter
clear signal
H'FFFF
H'0000
TGF
TCFV
Prohibited
Figure 10-56 Contention between Overflow and Counter Clearing
Page 396 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010