HD64F2638F20J Datasheet, PDF (460/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Programmable Pulse Generator (PPG)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output
group 1 (pins PO7 to PO4). However, the chip has no pins corresponding to pulse output group 1.
Bit 5
G1INV
0
1
Description
Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output
group 0 (pins PO3 to PO0). However, the chip has no pins corresponding to pulse output group 0.
Bit 4
G0INV
0
1
Description
Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)
Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)
(Initial value)
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse
output group 3 (pins PO15 to PO12).
Bit 3
G3NOV
0
1
Description
Normal operation in pulse output group 3 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse
output group 2 (pins PO11 to PO8).
Bit 2
G2NOV
0
1
Description
Normal operation in pulse output group 2 (output values updated at compare match A
in the selected TPU channel)
(Initial value)
Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at
compare match A or B in the selected TPU channel)
Page 410 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010