HD64F2638F20J Datasheet, PDF (651/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Table 15-8 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
tcyc
Item Indication
Time Indication (at Maximum Transfer Rate) [ns]
I²C Bus
tSr/tSf
Specifi-
Influence cation
(Max.) (Min.)
φ=
5 MHz
φ=
8 MHz
φ=
φ=
10 MHz 16 MHz
tSCLHO 0.5 tSCLO
(–tSr)
Standard
mode
–1000
High-speed –300
mode
4000
600
4000
950
4000
950
4000
950
4000
950
tSCLLO 0.5 tSCLO
(–tSf )
Standard
mode
–250
High-speed –250
mode
tBUFO
0.5 tSCLO –
1 tcyc
( –tSr )
Standard
mode
High-speed
mode
–1000
–300
4700
1300
4700
1300
4750
4750
4750
4750
1000^*1 1000^*1 1000^*1 1000^*1
3800^*1 3875^*1 3900^*1 3938^*1
750^*1
825^*1
850^*1
888^*1
tSTAHO
0.5 tSCLO –
1 tcyc
(–tSf )
Standard
mode
High-speed
mode
–250
–250
4000
600
4550
800
4625
875
4650
900
4688
938
tSTASO 1 tSCLO
(–tSr )
Standard
mode
–1000
High-speed –300
mode
4700
600
9000
2200
9000
2200
9000
2200
9000
2200
tSTOSO
0.5 tSCLO +
2 tcyc
(–tSr )
Standard
mode
High-speed
mode
–1000
–300
tSDASO 1 tSCLLO^*2 – Standard
(master) 3 tcyc
mode
(–tSr )
High-speed
mode
–1000
–300
tSDASO
(slave)
1 tSCLL^*2 –
3 tcyc^*2
(–tSr )
Standard
mode
High-speed
mode
–1000
–300
4000
600
250
100
250
100
4400
1350
3100
400
3100
400
4250
1200
3325
625
3325
625
4200
1150
3400
700
3400
700
4125
1075
3513
813
3513
813
φ=
20 MHz
4000
950
4750
1000^*1
3950^*1
900^*1
4700
950
9000
2200
4100
1050
3550
850
3550
850
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 601 of 1458