HD64F2638F20J Datasheet, PDF (768/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Motor Control PWM Timer
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
19.2 Register Descriptions
19.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
—
IE
CMF CST
1
0
0
0
—
R/W R/W^* R/W
Note: * Only 0 can be written, to clear the flag.
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
PWCR is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and
counter (PWCNT) clock selection. It also contains a flag that indicates a compare match with the
cycle register (PWCYR). PWCR1 is the channel 1 register, and PWCR2 is the channel 2 register.
PWCR is initialized to H'C0 upon reset, and in standby mode, watch mode*, subactive mode*,
subsleep mode*, and module stop mode.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions only.
These functions cannot be used with the other versions.
Bits 7 and 6—Reserved: They are always read as 1 and cannot be modified.
Bit 5—Interrupt Enable (IE): Bit 5 selects enabling or disabling of an interrupt in the event of a
compare match with the PWCYR register for the corresponding channel.
Bit 5: IE
0
1
Description
Interrupt disabled
Interrupt enabled
(Initial value)
Page 718 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010