HD64F2638F20J Datasheet, PDF (295/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 9 I/O Ports
Port 3 Open Drain Control Register (P3ODR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯ P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Undefined Undefined 0
0
0
0
0
0
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P35 to P30).
By setting P3ODR to 1, the port 3 pins become an open drain out, and when cleared to 0 they
become CMOS output.
P3ODR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state
is maintained in software standby mode.
9.3.3 Pin Functions
The port 3 pins double as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1)
external interrupt input pins (IRQ4 and IRQ5), and IIC I/O pins* (SCL0, SDA0, SCL1, and
SDA1). The functions of port 3 pins are shown in table 9-5.
Note: * Available when using I²C bus interface as an option in the H8S/2638, H8S/2639, and
H8S/2630 (the product equipped with the I²C bus interface is the W-mask version).
REJ09B0103-0800 Rev. 8.00
May 28, 2010
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