HD64F2638F20J Datasheet, PDF (113/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 2 CPU
2.8 Processing States
2.8.1 Overview
The CPU has five main processing states: the reset state, exception handling state, program
execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the
processing states. Figure 2-15 indicates the state transitions.
Processing
states
Reset state
The CPU and all on-chip supporting modules have been
initialized and are stopped.
Exception-handling
state
A transient state in which the CPU changes the normal
processing flow in response to a reset, trace, interrupt,
or trap instruction.
Program execution
state
The CPU executes program instructions in sequence.
Bus-released state
The external bus has been released in response to a bus
request signal from a bus master other than the CPU.
Sleep mode
Power-down state
CPU operation is stopped
to conserve power.*
Software standby
mode
Hardware standby
mode
Note: * The power-down state also includes a medium-speed mode, module stop mode,
subactive mode, subsleep mode, and watch mode.
See section 23A and 23B, Power-Down Modes, for details.
Figure 2-14 Processing States
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 63 of 1458