HD64F2638F20J Datasheet, PDF (344/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 9 I/O Ports
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
9.11.2 Register Configuration
Table 9-20 shows the port F register configuration.
Table 9-20 Port F Registers
Name
Port F data direction register
Abbreviation R/W
PFDDR
W
Port F data register
PFDR
R/W
Port F register
PORTF
R
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Initial Value
B'10000**0^*2/
B'00000**0^*2
B'00000**0
Undefined
Address^*1
H'FE3E
H'FF0E
H'FFBE
Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR —
— PF0DDR
Modes 4 to 6
Initial value :
1
0
0
0
0
undefined undefined
0
R/W
:W
W
W
W
W
—
—
W
Mode 7
Initial value :
0
0
0
0
0
undefined undefined
0
R/W
:W
W
W
W
W
—
—
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to B'10000**0 in modes 4 to 6,
and to B'00000**0 in mode 7. It retains its prior state in software standby mode. The OPE bit in
SBYCR is used to select whether the bus control output pins retain their output state or become
high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR) (in the 8-bit mode,
pin PF3 is designated by PFDDR).
Page 294 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010