HD64F2638F20J Datasheet, PDF (833/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21A ROM
(H8S/2636 Group)
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
2. Immediately after exception handling (excluding a reset) during programming/erasing
3. When a SLEEP instruction (including software standby) is executed during
programming/erasing
4. When the CPU releases the bus to the DTC
Error protection is released only by a reset and in hardware standby mode.
Figure 21A-14 shows the flash memory state transition diagram.
Program mode
Erase mode
RES = 0 or HSTBY = 0
Reset or standby
(hardware protection)
RD VF PR ER FLER = 0
RD VF PR ER FLER = 0
Error
occurrence
Error occurrence
(software standby)
RES = 0 or
HSTBY = 0
RES = 0 or
HSTBY = 0
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Error protection mode
Software
standby mode
Error protection mode
(software standby)
RD VF PR ER FLER = 1
Software standby
mode release
RD VF PR ER FLER = 1
FLMCR1, FLMCR2, (except bit FLER)
EBR1, EBR2 initialization state
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
Figure 21A-14 Flash Memory State Transitions
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 783 of 1458